Ram

ABSTRACT

A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional of U.S. application Ser. No.10/255,392, filed Sep. 26, 2002 entitled RAM, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to the forming of RAMs inintegrated form. More specifically, the present invention relates to theforming of dynamic random access memories (DRAMs).

[0004] 2. Discussion of the Related Art

[0005] Generally, a DRAM is formed of an array of elementary memorycells located at the intersection of rows (word lines) and columns (bitlines). Each elementary cell is formed of a capacitive memory point(capacitor) and of an element for controlling this memory point,generally, a MOS transistor. The gate of the MOS transistor forms theword line of the cell. The source or drain region of the controltransistor is in contact with a first electrode of the capacitor, theother electrode or plate of which is common to all cells in at least onecolumn. The drain or source region of the control transistor is integralwith a bit line common to all cells in a column.

[0006] Constantly, the amount of elementary cells integrated on a givensilicon surface area is desired to be increased as much as possible. Forthis purpose, it is desired to reduce to the smallest possible thedimensions of an elementary cell. The smallest possible dimension for aconductive line is designated with reference F. This minimum dimensionis also called the minimum rule, since it corresponds to a drawing ruleimposed to the designer by a used manufacturing technology. Square F2 ofminimum rule F thus is the minimum surface area or unity surface area ofa pattern. Elementary cells having a surface area which is four timesthe unity surface area could theoretically be formed. However, inpractice, the cells have a much larger size.

[0007] A DRAM cell having an integration surface area which is only sixtimes the unity surface area (6 F²) has been proposed in review 2000IEEE, IEDM, pp. 349 to 352, published on Dec. 10, 2000, in article “Anorthogonal 6F² Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM”by C. J. Radens et al.

[0008]FIG. 1 illustrates, in a partial simplified top view, a memoryincluding such 6F² cells. More specifically, FIG. 1 illustrates twoparallel bit lines BL1, BL2. Each bit line BL1, BL2 has the width ofminimum rule F, and is separated from a next bit line BL2, BL1, by twice2F the minimum rule. Two parallel word lines WL1 and WL2 are separatedby this same minimum rule F. Memory points C11, C12, C21, and C22 areformed, as described hereafter in relation with FIGS. 2A to 2E and 3,under the intersections of bit lines BL1, BL2 and word lines WL1, WL2.The 6F² cell finally includes between every two word lines WL1, WL2between two memory points C11 and C21, C12 and C22, a bit line contactBLC1, BLC2.

[0009]FIGS. 2A to 2E illustrate, in a partial simplified cross-sectionview along axis A-A of FIG. 1, that is, an axis running in bit line BL2,successive steps of a method for forming such a 6F² cell. FIG. 3 is across-section view along axis B-B of FIG. 1, parallel to axis A-A, abovememory points C12 and C22 sharing the same bit line BL2, but outside ofthis bit line. FIG. 3 corresponds to an intermediary step between thoseillustrated in FIGS. 2C and 2D.

[0010] As illustrated in FIG. 2A, an N-type doped region 2 is firstformed, generally by epitaxy, on a semiconductor substrate 1, typicallymade of silicon, of a first conductivity type, conventionally type P.Region 2 is buried under a P-type surface region or well 3. Buriedregion 2 is intended to be used as a plate electrode of the memorypoint. Then, a trench 4 is dug into well 3, region 2, and substrate 1.The definition of the location and of the dimensions of trench 4 isperformed by means of the first mask.

[0011] A silicon oxide insulating ring 5 is then formed on a highportion of the walls of trench 4. An insulator 6 with a high electricpermittivity is then deposited on the bottom and walls of trench 4. Aheavily-doped N-type peripheral region 7 is formed in substrate 1 andregion 2, around the low portion of trench 4. Then, a conductivematerial 8, generally polysilicon, is deposited at the bottom of trench4. An elementary memory point having an electrode 7 connected by region2 to the similar electrodes of several cells and separated by adielectric 6 from a second electrode 8 specific to each memory point isthus formed.

[0012] At the next steps, illustrated in FIG. 2B, insulator 5 is removedfrom a high portion of one of the walls of trench 4, for example, theleft-hand wall. A conductive material 9, identical to material 8,generally polysilicon, is deposited and etched. Material 9 is in contactby its low portion with electrode 8. This low portion is insulated fromthe peripheral silicon (well 3, region 2) by ring 5. Material 9 is incontact in its high portion with well 3 along the wall from whichinsulator 5 has been removed. A heavily-doped N-type region 10 is formedin well 3 by diffusion from material 9.

[0013] Then, a thick insulator is formed on material 9. Insulator 11aims at insulating material 9 from any parasitic coupling withconductive structures formed at the next steps in the upper portion oftrench 4. Region 10, which is diffused from material 9, extends to thetop of the structure (surface of well 3) beyond thick insulator 11.

[0014] At the newt steps, illustrated in FIG. 2C, a thin insulator 12 isformed on the exposed wall of trench 4 and on the planar horizontalsurface of well 3. A heavily-doped N-type region 13 is then implanted atthe surface of well 3. Then, a conductive material 14, generallypolysilicon, is deposited. Material 14 is intended to be used as thecontrol transistor gate, insulator 12 being the gate insulator betweengate 14 and vertical well 3.

[0015] The result of next steps is illustrated in FIG. 3, which is across-section view along line B-B of FIG. 1. Well 3 has been dug into,as well as a portion of the multiple-layer formed in trench 4, to open ashallow insulating trench 15 (STI) filled with an insulator. Insulatingtrench 15 is formed to extend in depth beyond contact level 9 and toreach insulating ring 5. The second mask used to dig into insulatingtrench 15 must thus be precisely aligned with respect to the first maskused (FIG. 2A) to dig into trench 4. The forming of insulating trenches15 enables individualizing neighboring elementary cells.

[0016] As illustrated in FIG. 2D, gate 14 is then completed, forexample, by forming a tungsten silicide layer 16 and an insulating layer171. Then, by means of a third mask which must be precisely aligned withrespect to the first and second masks, the multiple layer formed oflayers 14-16-171 is etched to define (individualize) the word lines ofeach of the elementary cells. Gate 14-16-171 is then provided on itsvertical walls with an insulating structure 172, generally of samenature as insulating layer 171. A thick interlevel insulating ordielectric layer 18 is then deposited so that its surface issubstantially planar. Interlevel dielectric 18 is of different naturethan the insulator forming layer 171 and vertical insulating structure172, to be selectively etchable with respect thereto.

[0017] At the next steps, illustrated in FIG. 2E, the method carries onwith the opening of interlevel dielectric 18 by means of a fourth mask,to partially expose surface regions 13. The fourth mask must again beprecisely aligned with respect to the three preceding masks. Aconductive material 19 is deposited on dielectric 18 to at least fillthe openings. Finally, material 19 is etched by means of a fifth mask todefine above dielectric 18 bit line contacts with source or drainregions 13. The central contact illustrated in FIG. 2E is contact BLC2of FIG. 1. The alignment of the fifth mask must also be preciselyperformed with respect to the preceding masks.

[0018] A memory point having, as a control element, a MOS transistorwith a substantially vertical channel has thus been formed, asillustrated in FIG. 2E. Heavily-doped surface region 13 forms a sourceregion of the transistor. The drain region of the transistor is formedby region 10. This transistor includes a control gate 14 insulated fromthe channel region by a thin insulator 12. This control transistorenables possibly putting in contact a bit line 19 with first electrode9-8 of a memory point having its second electrode or plate correspondingto regions 7 and 2.

[0019] Such a formation method is relatively complex due to the fivemasks successively used, which must be precisely aligned with respect toone another.

[0020] The use of such masks further results in the forming ofelementary cells having six times the unity surface area, instead offour times as would theoretically be possible.

SUMMARY OF THE INVENTION

[0021] The present invention accordingly aims at providing a DRAM havingits elementary cells occupying a smaller semiconductor surface area.

[0022] The present invention also aims at providing such a memory whichis simpler to form than a memory taking up a larger surface area.

[0023] To achieve these and other objects, the present inventionprovides a method for forming in monolithic form a DRAM-type memory,including the steps of:

[0024] forming, on a single-crystal semiconductor substrate, parallelstrips including a lower insulating layer, a strongly-conductive layer,a single-crystal semiconductor layer, and an upper insulating layer;

[0025] digging, perpendicularly to the strips, into the upper insulatinglayer and into at least a portion of the semiconductor layer, first andsecond parallel trenches, each of the first and second trenches beingshared by neighboring cells;

[0026] forming, in each of the first trenches, a first conductive linesaccording to the strip width;

[0027] forming, in each of the second trenches, a pair of seconddistinct parallel conductive lines, insulated from the layers peripheralto the second trench;

[0028] filling the first and second trenches with an insulatingmaterial;

[0029] removing the remaining portions of the upper insulating layer;and

[0030] depositing a conductive layer.

[0031] According to an embodiment of the present invention, the formingof the parallel strips includes the steps of:

[0032] forming on a first single-crystal semiconductor substrate asingle-crystal semiconductor layer resting on a first insulating layer;

[0033] forming, on the semiconductor layer, a strongly-conductive layer,then a second insulating layer;

[0034] digging parallel trenches into the second insulating layer, thestrongly-conductive layer, and the semiconductor layer, to partiallyexpose the first insulating layer;

[0035] turning over and gluing the structure thus obtained on a secondsubstrate; and

[0036] removing the first substrate, whereby the first insulating layerbecomes the upper layer of the structure thus formed and the secondinsulating layer becomes the lower layer underlying the semiconductorlayer.

[0037] According to an embodiment of the present invention, the firstand second trenches are dug into the upper insulating layer and at leasta portion of the semiconductor layer so that the first trenches have aminimum width, and the second trenches have a width which is twice thatof the first trenches, two neighboring trenches being separated by aminimum interval, each first trench being surrounded with two secondtrenches and each second trench being surrounded with two firsttrenches.

[0038] According to an embodiment of the present invention, the firstand second trenches are dug into to maintain between thestrongly-conductive layer and the bottom of each of the first and secondtrenches a given thickness of the semiconductor layer.

[0039] According to an embodiment of the present invention, the firstand second trenches are dug into to partially expose thestrongly-conductive layer.

[0040] According to an embodiment of the present invention, the firstconductive lines at the bottom of each first trench and the pairs ofsecond insulated conductive lines at the bottom of the second trenchesare formed simultaneously.

[0041] According to an embodiment of the present invention, thesimultaneous forming of the first lines and of the pairs of second linesat the bottom of the first and second trenches includes the steps of:

[0042] depositing at the bottom and on the walls of the first and secondtrenches an insulating layer;

[0043] conformally depositing a conductive material to at least fill thefirst trench; and

[0044] removing the conductive material from the surface of the firstinsulating layer.

[0045] According to an embodiment of the present invention, the linesformed at the bottom of the first trenches are not insulated from theperipheral semiconductor and/or conductor layers.

[0046] According to an embodiment of the present invention, the forming,at the bottom of the first trenches, of lines which are not insulatedfrom the peripheral semiconductor and/or conductive layers includes thesteps of:

[0047] conformally depositing an insulating material at the bottom andon the walls of the first and second trenches;

[0048] conformally depositing a first sub-layer of a conductivematerial;

[0049] performing a directional bombarding so that the conductivematerial is only bombarded on its sides in the second trenches;

[0050] removing by selective etching the sole non-bombarded portions ofthe conductive material in the first trenches;

[0051] removing the portions thus exposed of the insulating materialpreviously deposited at the bottom of the first and second trenches;

[0052] depositing a second sub-layer of the conductive material to atleast fill the first trenches; and

[0053] removing the conductive material from the surface of the firstinsulating layer.

[0054] According to an embodiment of the present invention, the methodfurther includes, after the step of deposition of a conductive layer,the steps of:

[0055] level trimming, which results in the forming, between a first anda second neighboring trenches, of independent conductive surfaces incontact with the surface of the semiconductor layer;

[0056] depositing over the entire structure a thin dielectric with ahigh permittivity; and

[0057] depositing over the entire structure a conductive layer.

[0058] The present invention also provides a DRAM, including:

[0059] parallel strips formed of the stacking, on a single-crystalsemiconductor substrate, of an insulating layer of a strongly-conductiveline, and of a semiconductor layer;

[0060] first conductive lines running perpendicularly to the strips,each in a first relatively thin trench dug into at least a portion ofthe semiconductor layer;

[0061] pairs of second conductive lines parallel to each other and tothe first lines, each pair of second lines running in a secondrelatively wide trench dug into at least a portion of the semiconductorlayer between two first trenches; and

[0062] conductive surfaces of unity area resting on the semiconductorlayer, these surfaces being defined at the surface of the strips by theintervals separating a first and a second neighboring strips.

[0063] According to an embodiment of the present invention, the firstand second trenches do not reach the underlying strongly-conductivelines, the second lines being insulated with respect to the peripheralsemiconductor layer and forming the word lines of the memory, thestrongly-conductive lines forming the bit lines of the memory, and thesurfaces of unity area forming first individual electrodes of the memorypoints of the memory.

[0064] According to an embodiment of the present invention, the firstlines are reference biasing lines of the semiconductor layer,independent from the line pairs running in the second trenches.

[0065] According to an embodiment of the present invention, the firstlines are insulated from at least the peripheral semiconductor layer.

[0066] The foregoing objects, features and advantages of the presentinvention will be discussed in detail in the following non-limitingdescription of specific embodiments in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0067]FIG. 1 illustrates, in a partial simplified top view, a memoryincluding known DRAM cells;

[0068]FIGS. 2A to 2E illustrate, in a partial simplified cross-sectionview along axis A-A of FIG. 1, successive steps of a method for forminga known DRAM cell;

[0069]FIG. 3 illustrates, in a partial simplified cross-section viewalong axis B-B of FIG. 1, intermediary steps between the stepsillustrated in FIGS. 2C and 2D;

[0070]FIGS. 4A to 4C illustrate, in a partial simplified cross-sectionview, steps of the forming of a DRAM array according to an embodiment ofthe present invention;

[0071]FIG. 5 illustrates, in a partial simplified top view, the state ofa DRAM array according to the present invention at an intermediary stateof its forming;

[0072]FIGS. 6A to 6D illustrate, in partial simplified cross-sectionviews, steps of the forming of a DRAM according to an embodiment of thepresent invention subsequent to the steps illustrated in FIG. 4C;

[0073]FIG. 7 illustrates, in a partial simplified top view, anembodiment of a memory according to the present invention; and

[0074]FIG. 8 illustrates, in a partial simplified cross-section view, aDRAM array according to another embodiment of the present invention.

DETAILED DESCRIPTION

[0075] For clarity, the same elements have been designated with the samereferences in the different drawings. Further, as usual in therepresentation of integrated circuits, the different drawings are not toscale.

[0076] The DRAM cell manufacturing method according to the presentinvention starts, as illustrated in FIG. 4A, with the forming, on asingle-crystal semiconductor substrate 20, of a single-crystalsemiconductor layer 22 on insulator (SOI). A multiple-layer formed of afirst insulating layer 21 and of a semiconductor layer 22 is thusobtained on substrate 20. A strongly-conductive layer 23, preferably ametal or a metal alloy, is then formed on semiconductor layer 22. Asecond, relatively thick, insulating layer 24 is then deposited. Secondinsulating layer 24 is deposited so that its upper surface issubstantially planar.

[0077] Then, a third sacrificial insulating layer 25 is deposited.Parallel trenches 26 are dug into the multiple-layer formed ofsingle-crystal layer 22, of layer 23, and of insulating layer 24 bymeans of a first mask, to partially expose insulating layer 21. Trenches26 have a minimum width, equal to drawing rule F, and separate stripshaving an also minimum width, equal to rule F.

[0078] At the next steps, illustrated in FIG. 4B, the entire structureshown in FIG. 4A is turned over and glued on a second single-crystalsemiconductor substrate 27. A series of strips formed of insulatinglayer 24, conductive layer 23, and semiconductor layer 22 supportingfirst insulating layer 21 and first substrate 20 are thus obtained onsecond substrate 27.

[0079] According to the embodiment shown in FIG. 4B, before turning overthe structure of FIG. 4A, trenches 26 are filled with an insulator 28.After the deposition of insulator 28 and before turning over, the entirestructure is leveled, for example by means of a chem-mech polishing, toguarantee a substantially planar surface to ease the gluing on secondsubstrate 27. According to an alternative, not shown, the intervals(trenches 26) between distinct strips are maintained empty.

[0080] Then, as illustrated in FIG. 4C, first substrate 20, now at thetop of the structure, is removed, for example by selective wet etch.First insulating layer 21 then is the upper layer of the structure.Parallel strips, each of which includes on a lower insulator 24 aconductive layer 23, a single-crystal semiconductor column 22, and anupper insulating layer 21, are thus formed.

[0081] A fourth insulating layer 30 is then deposited on firstinsulating layer 21. The insulator forming layer 30 is different fromthe insulator forming layer 21. Indeed, insulator 30 is a sacrificialinsulator intended to be used as a mask.

[0082] As partially and schematically illustrated in top view in FIG. 5,parallel independent conductive lines formed by the portions ofstrongly-conductive layer 23 have thus been formed. Eachstrongly-conductive line 23 underlies a single-crystal column 22. Twoneighboring columns are separated by an insulator which is either air,or a material 28.

[0083]FIGS. 4A to 4C correspond to cross-section views along axis C-C ofFIG. 5, that is, the axis perpendicular to the extension axis of lines23. The rest of the process will now be described, in relation withFIGS. 6A to 6D, along an axis perpendicular to axis C-C, that is, anaxis parallel to the extension axis of strips 24-23-22-21-30. Morespecifically, as illustrated in FIG. 5, an axis D-D running in such astrip 24-23-22-21-30 will be followed.

[0084]FIG. 6A partially and schematically shows such a cross-sectionalong axis D-D at the step following the deposition of the fourth layer30 previously described in relation with FIG. 4C. According to thepresent invention, the fourth and first insulating layers 30 and 21, aswell as single-crystal column 22, are then dug into by means of a secondmask, to form parallel trenches. The trench pattern according to thepresent invention provides the forming of parallel trench pairs 31, 32.First trenches 31 have an opening (width) reduced to the minimumpossible dimension F for a conductive line in a considered technology.Each first trench 31 is separated from second neighboring trenches by aninterval substantially equal to this minimum dimension (or rule) F.Second trenches 32 are twice as wide (2F) as first trenches 31. As willbetter appear from the following description, each trench 31 or 32 isshared between two neighboring cells. Two first narrow trenches 31surrounding a second wide trench 32 have been shown in FIGS. 6A-6D.

[0085] The alignment of the first digging mask of the first and secondtrenches 31 and 32 sets no specific alignment constraint with respect tothe first digging mask of trenches 26 (FIG. 4A). More specifically,trenches 31, 32 must be formed to be perpendicular to lines 23, that is,along axis C-C of FIG. 5. As will better appear from the followingdescription, there is no lateral alignment constraint (along axis D-D ofFIG. 5).

[0086] After removal of fourth insulator 30, as illustrated in FIG. 6B,a fifth insulating layer 33 is formed on the walls and the bottom of atleast second wide trenches 32. Layer 33 preferably is a thin insulator.

[0087] According to an embodiment, layer 33 is also formed on the wallsand the bottom of each first narrow trench 31.

[0088] Then, a layer of a conductive material is conformally deposited.This layer is etched to be removed from the surface of insulating layer21. This removal is performed by an anisotropic etching. Thus, theconductive material is maintained in place in the first and secondtrenches 31 and 32 at the locations where it is the thickest and removedfrom the locations where it is thinner. A continuous conductive line 341is then formed at the bottom of each narrow trench 31. At the bottom ofeach wide trench 32, only two distinct lateral lines 342 and 343 remainin place. Each line 342 and 343 rests on the bottom and one of the wallsof trench 32, and is insulated from active substrate 22 by an insulatinglayer 33. Lines 341, 342, and 343 perpendicularly extend to reachunderlying line 23. As should be understood by those skilled in the art,trenches 31 and 32 are dug into previously-formed parallel multiplestrips 24-23-22-21. Each lines 341, 342, or 343 thus runs above alllines 23. This crossing occurs even if the digging mask of the first andsecond trenches 31 and 32 is laterally shifted along axis D-D of FIG. 5.

[0089] Then, as illustrated in FIG. 6C, a sixth insulator 35 isdeposited over the entire structure. Insulator 35 is deposited to filltrenches 31 and 32. For example, after deposition of a relatively thickinsulating layer, a level trimming by chem-mech polishing is carried outto expose the remaining portions of first insulating layer 21. Then,first insulating layer 21 is removed. Portions of single-crystalsemiconductor layer 22 are thus exposed. Each of these portions isdelimited by a first narrow trench 31, by a second trench 32 along axisD-D of FIG. 5, and by interstrip insulator 28 along axis C-C of FIG. 5.The exposed portions have a surface area equal to the product of theinterval between first and second trenches by the interstrip interval.They thus have a unity surface area.

[0090] A conformal deposition of a layer 36 of a conductive material isthen performed. The deposition of layer 36 is followed by a chem-mechpolishing. A conductive surface 36 in contact with active substrate 22is thus individualized between two trenches 31 and 32.

[0091] Finally, as illustrated in FIG. 6D, the structure is completed bya partial etching of sixth insulator 35, by the conformal deposition ofa layer of a dielectric having a high electric permittivity 37, and bythe deposition of a conductive layer 38. Conductive layer 38, preferablysimilar to material 36, is deposited so that its upper surface isplanar. For this purpose, it will be possible to perform, afterdeposition of a relatively thick layer 38, a chem-mech polishing.

[0092] A DRAM having columns formed by strips and having rows formed bythe lines formed in the second trenches has thus been formed. FIG. 6Dillustrates two cells of a memory according to an embodiment of thepresent invention. Conductive surfaces of unity area 36 form the firstindividual electrodes of different memory points. The inter-electrodeinsulator is dielectric 37. The second electrode common to severalmemory points is layer 38.

[0093] The channel area of the control transistor of each memory pointis vertical, in single-crystal column 22. It is defined by a gate 342 or343 and a gate insulator formed by fifth insulator 33. A drain or sourceregion is located at the surface of column 22, in contact withconductive surface 36. A source or drain region is buried in column 22close to and in contact with line 23. The bit line is formed by line 23.It is common to all cells in a strip.

[0094] The forming of the different channel, drain, and source regionsis performed by implantation in the different steps of formation. Forexample, upon forming by epitaxy of the single-crystal semiconductorlayer 22 (FIG. 4A), a well doping is performed in situ. Then, the sourceor drain region intended to be (after the subsequent turning overdescribed in relation with FIG. 4B) at the bottom of the column isformed by successive low density deposition (LDD) and high densitydeposition (HDD) before deposition of strongly-conductive layer 23.After the opening (FIG. 6A) of the pairs of parallel trenches 31 and 32,the well implantation is completed to give the transistor channel theappropriate doping. Then, after deposition of the conductive material inthe pairs of parallel trenches 31 and 32, but before its etching (FIG.6B) to form lines 341, 342, and 343, this material may be doped. Afterthe etching, a low-density doping (LDD) of the drain or source regionformed at the surface of column 22 is performed. Finally, after removalof first insulating layer 21 and before deposition (FIG. 6C) ofconductive surface 36, a high-density doping (HDD) of the drain orsource region formed at the surface of column 22 is performed.

[0095] Further, the present invention also provides a reference biasingof the channel region by line 341 formed in narrow trench 31.

[0096] It should be noted that each trench 31, 32 is advantageouslyshared by two memory cells. FIG. 6D illustrates, for example, twocomplete memory points on either side of the largest trench 32 at thecenter of the drawing. Each of distinct lines 342, 343 formed in thistrench is the word line of a distinct elementary cell. Similarly, as forreference biasing line 341 of column 22, it ensures the biasing eitherdirectly, or by influence, as will be described in detail hereafter, oftwo vertical “wells” of intermediary control transistors between twotrenches 31 and 32 and underlying two distinct memory points 36-37-38.Such a sharing is illustrated in FIG. 6D by the vertical dotted linesrunning at the center of the first and second trenches.

[0097] Due to such a sharing, a dimension of a cell according to thepresent invention is the sum of half of the width of a first narrowtrench 31 of the interval separating a first narrow trench 31 from awider trench 32, and of half of the width of a second trench 32. Thiswidth is thus equal to the sum of half of the minimum rule and of halfof twice the minimum rule, that is, twice and a half the minimum rule(2.5 F). The other dimension of a cell according to the presentinvention is the standard interval between two bit lines previouslyillustrated in relation with FIG. 5, that is, twice (2 F) the minimumrule. The surface area taken up by a cell according to the presentinvention is thus five times the unity surface area (2.5 F*2 F=5 F2).

[0098]FIG. 7 illustrates, in a simplified partial top view, a portion ofa DRAM array according to the embodiment of the present inventionpreviously described in relation with FIGS. 4A-C, 5, and 6A-D. Such amemory thus includes parallel bit lines 23 buried under a semiconductorlayer (22, FIGS. 4 and 6) in which are formed at the bottom and at thesurface of the source and drain regions of a vertical transistor. Twoneighboring bit lines 23 are insulated by an insulator 28. Gates 342,343 of the memory point (word line) control vertical transistors areperpendicular to the bit lines. Each pair of neighboring cells is alsoassociated with a reference biasing line 341 of the substrate parallelto the word lines. Each memory point of the array is interposed betweena word line and a reference line, above a bit line 23. Dimensions 2F*2.5 F of a cell according to the present invention are clearly shownon the top view of FIG. 7.

[0099] An advantage of a method according to the present invention isthat it requires use of two masks only (opening of trenches 26, openingof trenches 31, 32). All other processings are self-aligned.

[0100] Another advantage is that the alignment of the second mask withrespect to the first mask is not critical. More specifically, the onlyconstraint to be respected is a rule of perpendicularity of the twomasks, which is easily acquired with a restricted number of referencemarks. A possible lateral misalignment has no incidence upon the formingof the structure. Indeed, all rows (second trenches 32) crossing all thecolumns (strips 24-23-22) of the array define same unity surface areasspecific to the forming of independent contacts 36 after removal offirst insulating layer 21.

[0101] Since no alignment constraint is to be taken into account, noguard is necessary and the surface area of an elementary cell can bereduced.

[0102] The surface area of a memory cell according to the presentinvention obtained with such a simplified method is advantageouslyreduced, as described previously, to five times, 5 F2, the unity surfacearea.

[0103] As a non-limiting example, considering that, in presenttechnologies, minimum rule F is on the order of from 0.16 to 0.30 μm,for example, approximately 0.20 μm, the natures and thicknesses of thevarious successively deposited layers are the following:

[0104] first and second substrate 20 and 27: single-crystalsemiconductor substrates, for example, silicon;

[0105] first insulating layer 21 formed of

[0106] ∘ silicon oxide (SiO₂), formed at the surface of first substrate20, of a thickness ranging between 40 and 400 nm, for example, on theorder of 100 nm, and

[0107] ∘ silicon nitride (Si₃N₄), of a thickness from 40 to 400 nm, forexample, 100 nm;

[0108] layer 22: single-crystal semiconductor, for example, silicon, forexample, of type P, of a thickness ranging between 0.3 and 0.8 μm, forexample, 0.5 μm;

[0109] strongly conductive layer 23: preferably, a metal, such as atungsten silicide layer (WSi₂), of a thickness ranging between 0.2 and0.3 μm, for example, on the order of 0.22 μm;

[0110] second insulating layer 24 formed of

[0111] ∘ silicon nitride, of a thickness ranging between 0.2 and 0.3 μm,and

[0112] ∘ silicon oxide, of a thickness ranging between 0.05 and 0.1 μm;

[0113] third (sacrificial) insulating layer 25: silicon oxide, of athickness on the order of 0.3 μm. In this case, the upper silicon oxideportion of multiple-layer 24 is removed upon removal of mask 25 (FIGS.4A-B);

[0114] interstrip insulator 28: silicon oxide;

[0115] fourth (sacrificial) insulating layer 30 made of silicon oxide,of a thickness on the order of 0.4 μm. In this case, the silicon oxideportion (initially, the lower portion, become the upper portion afterturning over and removal of first substrate 20; FIG. 4C) ofmultiple-layer 21 is removed upon removal of mask 30 (FIG. 6B);

[0116] trenches 31, 32: 0.4-μm depth;

[0117] fifth (gate) insulator 33: silicon oxide formed by thermaloxidation of substrate 22, of a thickness on the order of 3 nm;

[0118] conductive material of lines 341, 342, 343: polysilicon, of athickness depending on the considered technology. The depositedthickness will be at least equal to half F/2 of the minimum rule toguarantee in the selective etching previously described in relation withFIG. 6B the forming of a continuous line 341 at the bottom of each firstnarrow trench 31 of a width equal to minimum rule F. However, it will beascertained to avoid depositing to large a polysilicon thickness, toenable easy differentiation of the two distinct word lines 342, 343running in a wide trench 32. Column 22 being made of P-type silicon inthe considered example, reference biasing line 341 is biased to maintainthe “well” of the vertical control transistor at ground.

[0119] sixth (filling) insulator 35: silicon oxide;

[0120] conductive material 36: polysilicon of a thickness rangingbetween 30 and 300 nm, for example, on the order of 100 nm;

[0121] dielectric with a high electric permittivity 37: an insulatoradapted to forming the inter-electrode insulator of the memory point,for example, silicon nitride having a 5-nm thickness or tantalum oxide(Ta₂O₅) having a 10-nm thickness; and

[0122] plate electrode 38: polysilicon. After level trimming, it will beascertained to maintain a sufficient thickness to ensure the voltagedistribution homogeneity on the order of from 200 to 400 nm, forexample, approximately 250 nm.

[0123] According to an alternative, the result of which is illustratedin FIG. 8, after the step of deposition of a filling insulator 35described previously in relation with FIG. 6B, insulating material 35 isetched to be completely removed from first trenches 31, that is, toexpose the upper surface of each continuous line 341 formed at thebottom of each first trench 31. Given the increased amount of insulator35 in each second trench 32, the upper surfaces of lines 342 and 343 areexposed, but a portion of layer 35 remains at the bottom of each secondtrench 32, between lines 342 and 343. A thin layer of an insulator isthen conformally deposited. An anisotropic etching is then performed toremove this thin layer from the upper surface of first insulating layer21. The vertical walls of trenches 31 and 32 and of lines 342, 343 ofinsulating spacers 50 are thus left in place. A strongly-conductivelayer, for example, tungsten silicide 51, is then formed. Layer 51 isonly formed on the surfaces of lines 341, 342, and 343 included betweentwo spacers 50. Finally, the trenches are filled with an insulatingmaterial 55 as described previously in relation with FIG. 6B formaterial 35. Preferably, material 35, spacers 50, and filling material55 are of same nature, for example, silicon oxide. Then, the method forforming a memory according to the present invention carries on, forexample, as described previously in relation with FIGS. 6C and 6D.

[0124] An advantage of the specific embodiment described with FIGS. 4 to8 is that the transfer of an electron is performed linearly, along avertical line, in the semiconductor column 22 underlying electrode 36.The time of access to a memory cell according to the present inventionis then advantageously reduced with respect to a standard cell.

[0125] According to an alternative, not shown, it may be desirable notto keep fifth insulator 33 between column 22 and its reference biasingline 341. Then, it will be possible to deposit, after forming of fifthinsulator 33, a first thin sub-layer of the line conductor, and toperform a directional ion bombarding such that only the walls of thelarge trenches 32 are bombarded. Then, it is possible to implement aselective wet etching such that only the non-bombarded sub-layer isremoved in each first narrow trench 31. After such a removal, it ispossible to selectively remove fifth insulator 33 in the sole firsttrenches 31. Finally, a second sub-layer of the line material will bedeposited to form in each trench 31 a biasing line 341 directly incontact with the peripheral semiconductor column 22, and to increase thethickness of word lines 342 and 343 in each neighboring large trench 32.The method then carries on according to any of the embodiments describedin the present description. The reference biasing of semiconductorcolumn 22 by line 341 is then performed directly, and not by influenceas in the cases where an insulator is kept at the bottom of first trench31.

[0126] According to another alternative, if very small dimensions arereached, such as minimum dimension F, that is, on the order of 0.2 μm,it will be possible to do without a biasing control of column 22.However, first trenches 31 will then not be eliminated. Narrow trenches31 will be maintained at their minimum dimension F and the first andsecond trenches 31 and 32 will be opened to form, around asingle-crystal vertical well 22, a surrounding gate.

[0127] Of course, the present invention is likely to have variousalterations, modifications, and improvements which will readily occur tothose skilled in the art. In particular, those skilled in the art willknow how to adapt the doping levels and the implantation conditions toobtain a desired operation. Further, when a conductivity type has beenindicated, this conductivity type does not aim at limiting the presentinvention to this specific type. An operation with opposite conductivitytypes would be possible.

[0128] Further, when examples of materials and/or dimension have beenindicated, these examples do not aim at limiting the present invention.Only the insulating, semiconductor, or conductor character of thedescribed materials is to be considered and those skilled in the artwill know how to modify the materials used according to a consideredtechnology. Similarly, each single-layer may be replaced with amulti-layer structure. Similarly, any multilayer structure may bereplaced with a single-layer structure or a structure including moresub-layers than in the described examples.

[0129] Those skilled in the art will also know how to use substrate 27underlying a memory according to the present invention to form circuitsperipheral to this memory, outside of the area taken up by said memory.

[0130] Such alterations, modifications, and improvements are intended tobe part of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

What is claimed is:
 1. A method for forming in monolithic form aDRAM-type memory, including the steps of: forming, on a single-crystalsemiconductor substrate, parallel strips including a lower insulatinglayer, a strongly-conductive layer, a single-crystal semiconductorlayer, and an upper insulating layer; forming, perpendicularly to thestrips, in the upper insulating layer and in at least a portion of thesemiconductor layer, first and second parallel trenches, each of thefirst and second trenches being shared by neighboring cells; forming, ineach of the first trenches, a first conductive line according to a stripwidth; forming, in each of the second trenches, a pair of seconddistinct parallel conductive lines, insulated from the layers peripheralto the second trench; filling the first and second trenches with aninsulating material; removing the remaining portions of the upperinsulating layer; and depositing a conductive layer, wherein the firstand second trenches are formed in the upper insulating layer and atleast a portion of the semiconductor layer so that the first trencheshave a minimum width, and the second trenches have a width which istwice that of the first trenches, two neighboring trenches beingseparated by a minimum interval, each first trench being surrounded withtwo second trenches and each second trench being surrounded with twofirst trenches.
 2. The method of claim 1, wherein the forming of theparallel strips includes the steps of: forming on a first single-crystalsemiconductor substrate a single-crystal semiconductor layer resting ona first insulating layer; forming, on the semiconductor layer, astrongly-conductive layer, then a second insulating layer; formingparallel trenches in the second insulating layer, thestrongly-conductive layer, and the semiconductor layer, to partiallyexpose the first insulating layer; turning over and gluing the structurethus obtained on a second substrate; and removing the first substrate,whereby the first insulating layer becomes the upper layer of thestructure thus formed and the second insulating layer becomes the lowerlayer underlying the semiconductor layer.
 3. The method of claim 1,wherein the first and second trenches are formed to maintain between thestrongly-conductive layer and the bottom of each of the first and secondtrenches a given thickness of the semiconductor layer.
 4. The method ofclaim 1, wherein the first and second trenches are formed to partiallyexpose the strongly-conductive layer.
 5. The method of claim 1,including simultaneously forming the first conductive lines at thebottom of each first trench and the pairs of second conductive lines atthe bottom of the second trenches.
 6. The method of claim 5, wherein thesimultaneous forming of the first conductive lines and of the pairs ofsecond conductive lines at the bottom of the first and second trenchesincludes the steps of: depositing at the bottom and on the walls of thefirst and second trenches an insulating layer; conformally depositing aconductive material to at least fill the first trench; and removing theconductive material from the surface of the first insulating layer. 7.The method of claim 5, wherein the first conductive lines formed at thebottom of the first trenches are not insulated from the peripheralsemiconductor and/or conductor layers.
 8. The method of claim 7,including the steps of: conformally depositing an insulating material atthe bottom and on the walls of the first and second trenches;conformally depositing a first sub-layer of a conductive material;performing a directional bombarding so that the conductive material isonly bombarded on its sides in the second trenches; removing byselective etching the sole non-bombarded portions of the conductivematerial in the first trenches; removing the portions thus exposed ofthe insulating material previously deposited at the bottom of the firstand second trenches; depositing a second sub-layer of the conductivematerial to at least fill the first trenches; and removing theconductive material from the surface of the first insulating layer. 9.The method of claim 1, including, after the step of deposition of aconductive layer, the steps of: level trimming, which results in theforming, between first and second neighboring trenches, of independentconductive surfaces in contact with the surface of the semiconductorlayer; depositing over the entire structure a thin dielectric with ahigh permittivity; and depositing over the entire structure a conductivelayer.
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 14. A methodfor fabricating a monolithic DRAM-type memory, comprising: forming, on asingle crystal semiconductor substrate, parallel strips each including alower insulating layer, a strongly conductive layer, a single crystalsemiconductor layer, and an upper insulating layer; forming,perpendicular to the strips, in the upper insulating layer and at leasta portion of the semiconductor layer, first and second paralleltrenches, each of the first and second trenches being shared byneighboring cells; forming, in each of the first trenches, a firstconductive line; forming, in each of the second trenches, a pair ofsecond conductive lines, insulated from layers adjacent to the secondtrench; filling the first and second trenches with an insulatingmaterial; removing remaining portions of the upper insulating layer; anddepositing a conductive layer.
 15. A method as defined in claim 14,wherein the first and second trenches are formed so as to maintain agiven thickness of the semiconductor layer between the stronglyconductive layer and the bottom of each of the first and secondtrenches.
 16. A method as defined in claim 14, wherein the first andsecond trenches are formed so as to partially expose the stronglyconductive layer.
 17. A method as defined in claim 1, includingsimultaneously forming the first conductive lines in each first trenchand the pairs of second conductive lines in the second trenches.
 18. Amethod as defined in claim 17, wherein simultaneously forming the firstconductive lines and the pairs of second conductive lines includes:depositing an insulating layer on the bottom and on the walls of thefirst and second trenches; conformally depositing a conductive materialto at least fill the first trench; and removing the conductive materialfrom the surface of the first insulating layer.
 19. A method as definedin claim 14, including, after depositing a conductive layer, the stepsof: level trimming the structure to produce independent conductivesurfaces between first and second neighboring trenches; depositing overthe entire structure a thin dielectric with a high permittivity; anddepositing over the entire structure a further conductive layer.